module flow_con #(
    parameter CREDIT=4,
    parameter W=3 // 2^W > CREDIT
)(
    input clk,
    input rst,
    input f_e, // fifo empty
    output f_r, // fifo read enable
    input r_y // router yummy
);
    reg [W-1:0] su; // router space used;

    always @(posedge clk) begin
        if(rst)
            su<=0;
        else if(f_r && r_y)
            su<=su;
        else if(f_r)
            su<=su+1;
        else if(r_y)
            su<=su-1;
        else
            su<=su;
    end
    wire r_f= su==CREDIT; // router full

    assign f_r= ~r_f && ~f_e; 

endmodule

